1. Technical Field
Embodiments of the present invention generally relate to an integrated circuit, and more particularly, in one or more embodiments, to a data output circuit, a semiconductor memory apparatus including the same, and an operating method thereof.
2. Related Art
When a semiconductor memory apparatus responds to a read command from the corresponding memory controller, data bits may be read out not only from a single cell block but also from multiple cell blocks in response to address signals.
Multiple cell blocks (e.g., bank) are provided to be simultaneously working on different request. When data bits are read out from multiple cell blocks, the data bits may be transferred to a pipe latch unit through a global input/output line, which is shared by multiple cell blocks. In a semiconductor memory apparatus, an address strobe signal may be used to activate a particular address, and a data strobe signal may be used to capture data signals. A strobe signal may be generated by column signal for each cell block in response to a read command. A data strobe signal corresponding to a bust length may be generated in response to the strobe signal, and data transmitted through the global input/output line may be temporarily stored in the pipe latch unit in synchronization with the data strobe signal. The data stored in the pipe latch unit may be outputted in response to an output strobe signal.
To read out data without error, a margin between the timing of data transmission through the global input/output line and the timing of data strobe signal generation may be considered as an important factor.